Multi-Standard Fully Integrated 13.56-MHz Radio
(RFID Analog Front End and Data Framing Reader System)

The TRF7960/61 is an integrated analog front end and data framing system for a 13.56-MHz RFID reader system. Built-in programming options make it suitable for a wide range of applications both in proximity and vicinity RFID systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

A parallel or serial interface can be used for communication between the MCU and reader. When hardware encoders and decoders are used, transmission and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders/decoders can be bypassed in order for the MCU to process the data in real time. The transmitter has selectable output-power levels of 100 mW (20 dBm) or 200 mW (23 dBm) into a 50Ω load (at 5V supply) and is capable of ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise rejection for the complete reader system.

Data transmission comprises low-level encoding for ISO15693, modified Miller for ISO14443-A, high-bit-rate systems, Tag-it, and HF-EPC system coding. Included with the data encoding is automatic generation of SOF, EOF, CRC, and/or parity bits.

The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to cover a broad range of input subcarrier signal options. The received signal strength for AM and PM modulation is accessible via the RSSI register. The receiver output is selectable between a digitized subcarrier signal and any of eleven integrated subcarrier decoders (two for ISO15693 low bit rate, two for ISO15693 high bit rate, two for ISO14443, three for ISO14443 high bit rates, one for Tag-it, and one for HF-EPC system). Selected decoders also deliver bit stream and a data clock as outputs.

Features:
● Completely Integrated Protocol Handling (OSI Model Layer 3 and Below)
● Separate Internal High-PSRR Power Supplies for Analog, Digital, and
　PA Sections Provides Noise Isolation for Superior Read Range and Reliability
● Dual Receiver Input With AM and PM Demodulation to Minimize Communication Holes
　(Patent Pending).
● Receiver AM and PM RSSI
● Reader-to-Reader Anti-Collision
● High Integration Reduces Total BOM and Board Area
　- Single External 13.56-MHz Crystal Oscillator
　- MCU-Selectable Clock-Frequency Output of RF, RF/2, or RF/4
　- Adjustable 20-mA, High-PSRR LDO for Powering External MCU
● Easy to Use With High Flexibility
　- Auto-Configured Default Modes for Each Supported ISO Protocol
　- 11 User-Programmable Registers
　- Selectable Receiver Gain and AGC
　- Programmable Output Power (100 mW or 200 mW)
　- Adjustable ASK Modulation Range (8% to 30%)
　- Built-In Receiver Band-Pass Filter With User-Selectable Corner Frequencies
● Wide Operating Voltage Range of 2.7 V to 5.5 V
● Ultralow-Power Modes
　- Power Down < 1 μA
　- Standby 120 μA
　- Active (Rx only) 10 mA
● Parallel 8-Bit or Serial 4-Pin SPI Interface With MCU Using 12-Byte FIFO
● Ultra-small 32-Pin QFN Package (5mmx5mm)

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